(1) Filed of the Invention
The present invention relates to a multilayer substrate for a digital tuner and a multilayer substrate.
(2) Description of Related Art
Plural integrated circuits such as LSI-IC or the like have been mounted on a multilayer substrate. In this case, plural integrated circuits (for example, two circuits) are not mounted on the same layer but may be separately mounted on the upper-most layer (top-most layer) and on the lowest layer (bottom-most layer). The reason is that an integrated circuit is considered as a noise source. In order to avoid influence of noise, these circuits are not mounted on the same layer but on the top-most layer and the bottom-most layer for separation in distance. Moreover, on the inner sides of the top-most and bottom-most layers where the integrated circuits are mounted, a ground layer has respectively been formed, where a pattern for ground has been formed flat over its entire surface. That is, the ground layer can effectively prevent influence of noise from mutually effecting each integrated circuit respectively generated by each of the integral circuits, by introducing the structure explained above in order to fully show the effect for shielding noise.
Moreover, a structure of the multilayer substrate including in parallel a power source pattern region and a ground pattern region has also been proposed (for example, refer to JP-A 2004-281768 and JP-A 2002-158452).
In the multilayer substrate, it is also necessary to acquire a power source layer where a pattern for power source supply is arranged, in addition to a layer for mounting electronic components and the ground layer. Therefore, the above mentioned structure where the inner layers of the integrated circuit-mounted top-most layer and the bottom-most layer are assigned as ground layers allows increase in the number of layers to be laminated as the substrate. As a result, the structure explained above has been accompanied by a problem that the substrate manufacturing cost becomes higher.
Meanwhile, when a substrate with less number of layers to be laminated is employed for cost reduction purposes, there is no allowance for respective assigning of the inner layers of the integrated circuit-mounted top-most layer and the bottom-most layer as the ground layers, resulting in such a disadvantage that it is difficult to provide sufficient measures for noises.
Moreover, the reference documents explained above, JP-A 2004-281768 and JP-A 2002-158452 do not disclose the techniques for respectively mounting integrated circuits on the top-most and bottom-most layers among the layers forming a multilayer substrate. In addition, these patent documents disclose the techniques to provide a ground layer with only the pattern for ground formed over its entire surface. The number of layers of substrate increases to acquire such a ground layer and thereby manufacturing cost increases markedly. Moreover, since a couple of LSIs are mounted on the same layer in the reference document 1, no measure is taken for influence of noises to which both LSIs are subjected.